1. Field of the Invention
The present invention relates to a method of manufacturing a ferroelectric memory device capable of nonvolatile data storage utilizing a polarization of a ferroelectric layer.
2. Description of Related Arts
A ferroelectric memory device is a nonvolatile memory device in which a ferroelectric layer is used. When an electric field is applied to a ferroelectric layer, a polarization becomes complete in the ferroelectric layer, and the direction of the polarization is retained even after removing the electric field. By utilizing this, nonvolatile data storage can be performed.
FIG. 2 is a schematically sectional view showing the most basic structure of a ferroelectric memory element. A gate structure is formed, in which a ferroelectric layer 5 (F) and a metal layer 6 (M) as a gate electrode are stacked on the surface of a silicon substrate 1 (S). A pair of N-type diffused layers 2, 2 serving as a source and a drain are formed with the gate structure interposed therebetween. Thereby a MIS transistor using a ferroelectric layer as an insulating layer is fabricated.
By applying a voltage of, e.g. 5V between the metal layer 6 and the silicon substrate 1, an electric field oriented in a direction from the metal layer 6 toward the silicon substrate 1 or from the silicon substrate 1 toward the metal layer 6 is applied to the ferroelectric layer 5. This forms, in the ferroelectric layer 5, a polarization aligned with the direction of the applied electric field. The polarization is retained after removing the electric field applied between the metal layer 6 and the silicon substrate 1.
As a result, the surface of the silicon substrate 1 between the N-type diffused layers 2, 2 takes a state in which electrons are induced and a state in which holes are induced. Thereby, the threshold value of a voltage to be applied to the metal layer 6 for making conductive the pair of the N-type diffused layers 2, 2 changes between two kinds, namely, xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d in accordance with the direction of the polarization of the ferroelectric layer 5. Therefore, binary data of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d can be stored in a nonvolatile manner.
In the structure shown in FIG. 2, it is difficult to form a satisfactorily crystallized ferroelectric layer 5 on the silicon substrate 1. Further, this structure has another problem that the ferroelectric material is diffused in the silicon substrate 1. Accordingly, it has been proposed that another insulating layer 3 (I) is interposed between the silicon substrate 1 and the ferroelectric layer 5 as shown in FIG. 3.
In the structure shown in FIG. 3, it is necessary to obtain a favorable alignment in the surface boundary between the silicon substrate 1 and the insulating layer 3 and at the same time obtain a favorable alignment between the insulating layer 3 and the ferroelectric layer 5. Therefore, this structure has a problem that the material of the insulating layer 3 and the method for forming the same is strictly limited. Further, the insulating layer 3 does not have a satisfactory barrier effect for preventing the diffusion of the ferroelectric material.
On the other hand, in FIG. 4, a structure of a ferroelectric memory element is shown in which a metal layer 4 (M) is interposed between the insulating layer 3 and the ferroelectric layer 5 to form a gate structure. In this structure, since the alignment in the surface boundary between the insulating layer 3 and the ferroelectric layer 5 need not be considered, a satisfactorily crystallized insulating layer 3 can be formed on the silicon substrate 1 and at the same time, the ferroelectric layer 5 can be satisfactorily crystallized. Further, the metal layer 4 can prevent the diffusion of the ferroelectric material.
However, both of the structures shown in FIGS. 3 and 4 have the following problem in the manufacturing process thereof. The pair of N-type diffused layers 2, 2 serving as a source and a drain are formed by implanting N-type impurity ions in the silicon substrate 1 and thereafter activating the N-type impurities implanted in the surface of the silicon substrate 1 through activated annealing. The activated annealing comprises heating the silicon substrate 1 at a temperature of 900 to 950xc2x0 C. in a furnace for 1 to 2 hours. However, when the ferroelectric layer 5 is subjected to such a heat treatment, the polarization characteristics of the ferroelectric layer 5 are deteriorated.
In order to avoid this disadvantage, for example, a process of fabricating a MFMIS structure shown in FIG. 4 is required to comprise steps of fabricating a MIS transistor section, then activating the pair of N-type impurity diffused layers 2, 2, and thereafter forming a capacitor section in which the ferroelectric layer is interposed between the metal layers 4, 6.
FIG. 5 is a schematically sectional view for explaining a practical structural example of a ferroelectric memory element having the structure shown in FIG. 4. In this ferroelectric memory element, an insulating layer 3 and a metal layer 4a are stacked on the surface of the silicon substrate 1 to form a MIS gate structure, and a pair of N-type diffused layers 2, 2 are formed on both sides of the MIS gate structure respectively. Then, after the pair of N-type diffused layers are activated by activated annealing, a capacitor structure comprising a metal layer 4b, a ferroelectric layer 5 and a metal layer 6 is formed in a different position from that of the MIS transistor. And a connecting section 7 comprising wiring layers and plugs connects the metal layer 4a of the MIS transistor and the metal layer 4b on the capacitor side.
A disadvantage of the structure shown in FIG. 5 is that since the transistor section and the capacitor section are formed in the separate regions, the area occupied by a memory cell on the silicon substrate 1 becomes large and high level integration is hard to attain.
This disadvantage is somewhat decreased by adopting the structure shown in FIG. 6. In the structure shown in FIG. 6, a large-sized insulating layer 3 and a similarly large-sized metal layer 4 are stacked on a silicon substrate 1 to form a MIS structure, and thereafter, N-type impurities are implanted in the silicon substrate 1 and activated by annealing to form a pair of N-type diffused layers 2, 2 in the surface layer section of the silicon substrate 1. Then, a ferroelectric layer 5 and a metal layer 6 are formed and stacked in order on the silicon substrate 1.
When this structure is adopted, the area of the gate structure section in which the insulating layer 3 and the metal layer 4 are stacked is required to be larger than the area of the structure section in which the ferroelectric layer 5 and the metal layer 6 is stacked. This is so because it is necessary to secure a margin between a mask for patterning the gate structure section in which the insulating layer 3 and the metal layer 4 are stacked and a mask for patterning the structure section in which the ferroelectric layer 5 and the metal layer 6 are stacked.
Thus, when the structure shown in FIG. 6 is adopted, a large-sized area of gate structure section is also required. Therefore, in this case, the attainment of high level integration is limited.
An object of the present invention is to provide a method of manufacturing a ferroelectric memory device capable of advantageously attaining high level integration.
A method of manufacturing a ferroelectric memory device according to the present invention comprises steps of stacking a ferroelectric layer and a conductor layer on a semiconductor substrate in order, forming a gate structure section including the ferroelectric layer and the conductor layer by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into a pair of regions spaced apart from each other with the gate structure section interposed therebetween in a surface layer section of the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities so as to form a pair of impurity diffused layers in the pair of regions respectively.
According to the present invention, the gate structure section comprising the ferroelectric layer and the conductor layer is formed through a manufacturing process including the etching step using the common mask layer. And impurities are introduced into the semiconductor substrate in a self-aligning manner with respect to the gate structure section.
Accordingly, a transistor comprising the gate structure section including the ferroelectric layer and the conductor layer, and the impurity diffused regions formed with the gate structure interposed therebetween can be formed in a small area.
The impurities introduced into the semiconductor substrate are activated by annealing, whereby a pair of impurity diffused layers are formed with the gate structure section interposed therebetween. In this annealing step, the ferroelectric layer is crystallized at the same time.
According to the present invention, annealing for crystallizing the ferroelectric layer and annealing for activating the impurity ions are performed in a common step as abovementioned. As a result, the ferroelectric layer can be prevented from being deteriorated. Further, since the annealing of the semiconductor substrate can be completed only by once, heat damage to the semiconductor substrate can be reduced. Accordingly, the characteristics of the ferroelectric memory device can be improved. In addition, the manufacturing process can be simplified.
An advantage of this invention is that the crystallization of the ferroelectric layer and the activation of the impurities are performed in a common annealing step. By adopting such a step, the ferroelectric layer and the conductor layer constituting the gate structure section can be patterned by etching using a common mask layer, and though the impurity diffused layers are formed in a self-aligning manner using the gate structure section formed as abovementioned, the characteristics of the ferroelectric layer can be prevented from being deteriorated.
It is preferable that a method of manufacturing a ferroelectric memory device according to the present invention further comprises a step of forming an insulating layer on the semiconductor substrate before forming the ferroelectric layer.
According to this method, an insulating layer is interposed between the ferroelectric layer and the surface of the semiconductor substrate, and therefore, a gate structure section having a MFIS structure (see FIG. 3) can be formed.
Further, the method may further comprises a step of forming a different conductor layer after forming the insulating layer and before forming the ferroelectric layer, and this different conductor layer may be formed between the insulating layer and the ferroelectric layer.
According to this method, a gate structure section having so-called a MFMIS structure (see FIG. 4) can be formed. In this case, it is preferable to pattern the pair of conductor layers and the ferroelectric layer interposed therebetween using the common mask layer.
The annealing step for crystallizing the ferroelectric layer and activating the impurities preferably comprises lamp annealing. Thereby, the characteristics of the ferroelectric layer can be prevented from being deteriorated, unlike a case of the conventional activated annealing performed in a furnace. When the impurity diffused layers form a so-called shallow junction, the impurities implanted into the semiconductor substrate are sufficiently activated by a short time heat treatment such as lamp annealing, to form favorable impurity diffused layers.
The time period and the temperature of the lamp annealing are preferably determined on the basis of the material constituting the ferroelectric layer and the distance between the pair of the impurity diffused layers. That is, the conditions for performing the lamp annealing are adequately determined on the basis of the material of the ferroelectric layer and the channel length, so that both of the crystallization of the ferroelectric layer and the activation of the impurities implanted into the semiconductor substrate can be satisfactorily performed at the same time in the common annealing step.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention given with reference to the accompanying drawings.